Challenge: Compare your low-power/high-speed FPGA digit recognition design with the best in the world!
Hardware acceleration for machine-learning-based image recognition has become a very important topic in recent years. Especially when using FPGAs, one can obtain fast detection rates at high reliabilities without large infrastructure investments (as compared to an ASIC design) and still maintain low energy requirements. It allows for bringing fast and reliable image detection to edge devices. This has several advantages ranging from enhanced privacy, no communication overhead, lower latency, and lower energy requirements compared to cloud-based processing.
The aim of the challenge is to compare recent developments in FPGA-based hardware accelerators in terms of inference speed and low power while still providing high accuracy rates.
For this, the MNIST dataset of handwritten digits is used. MNIST is a widely recognized dataset that allows for easy comparison of different machine learning approaches.
